Other brands and names are the property of their respective owners

Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata

December 1995

INTEL CORPORATION 1995

Order Number 290435-005

28F008SA-L

8-MBIT (1 MBIT x 8) FLASHFILE

MEMORY

High-Density Symmetrically-Blocked
Architecture

Sixteen 64-Kbyte Blocks

Low-Voltage Operation

3 3V

0 3V or 5 0V

10% V

Extended Cycling Capability

10 000 Block Erase Cycles
160 000 Block Erase
Cycles per Chip

Automated Byte Write and Block Erase

Command User Interface
Status Register

System Performance Enhancements

RY BY

Status Output

Erase Suspend Capability

High-Performance Read

200 ns Maximum Access Time

Deep Power-Down Mode

0 20 mA I

Typical

SRAM-Compatible Write Interface

Hardware Data Protection Feature

Erase Write Lockout during Power
Transitions

Industry Standard Packaging

40-Lead TSOP 44-Lead PSOP

ETOX

III Nonvolatile Flash

Technology

12V Byte Write Block Erase

Intel's 28F008SA-L 8 Mbit FlashFile

Memory is the highest density nonvolatile read write solution for solid-

state storage The 28F008SA-L's extended cycling symmetrically-blocked architecture fast access time write
automation and very low power consumption provide a more reliable lower power lighter weight and higher
performance alternative to traditional rotating disk technology The 28F008SA-L brings new capabilities to
portable computing Application and operating system software stored in resident flash memory arrays provide
instant-on rapid execute-in-place and protection from obsolescence through in-system software updates
Resident software also extends system battery life and increases reliability by reducing disk drive accesses

For high-density data acquisition applications the 28F008SA-L offers a more cost-effective and reliable alter-
native to SRAM and battery Traditional high-density embedded applications such as telecommunications
can take advantage of the 28F008SA-L's nonvolatility blocking and minimal system code requirements for
flexible firmware and modular software designs

The 28F008SA-L is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assign-
ments simplify board layout when integrating multiple devices in a flash memory array or subsystem This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write The 28F008SA-L memory map consists of 16 separately erasable 64-Kbyte blocks

Intel's 28F008SA-L employs advanced CMOS circuitry for systems requiring low power consumption and
noise immunity Its 200 ns access time provides superior performance when compared with magnetic storage
media A deep power-down mode lowers power consumption to 0 66 mW typical thru V

crucial in portable

computing handheld instrumentation and other low-power applications The RP

power control input also

provides absolute data protection during system power-up down

Manufactured on Intel's 0 8 micron ETOX process the 28F008SA-L provides the highest levels of quality
reliability and cost-effectiveness

Other brands and names are property of their respective owners

28F008SA-L

PRODUCT OVERVIEW

The 28F008SA-L is a high-performance 8-Mbit
(8 388 608-bit) memory organized as 1 Mbyte
(1 048 576 bytes) of 8 bits each Sixteen 64-Kbyte
(65 536-byte)

blocks

are

included

the

28F008SA-L A memory map is shown in Figure 6 of
this specification A block erase operation erases
one of the sixteen blocks of memory in typically 2 0
seconds

independent of the remaining blocks

Each block can be independently erased and written
10 000 cycles Erase Suspend

mode allows sys-

tem software to suspend block erase to read data or
execute

code

from

any

other

block

the

28F008SA-L

The 28F008SA-L is available in the 40-lead TSOP
(Thin Small Outline Package 1 2 mm thick) and 44-
lead PSOP

(Plastic Small Outline) packages Pin-

outs are shown in Figures 2 and 4 of this specifica-
tion

The Command User Interface serves as the inter-
face between the microprocessor or microcontroller
and the internal operation of the 28F008SA-L

Byte Write and Block Erase Automation

allow

byte write and block erase operations to be execut-
ed using a two-write command sequence to the
Command User Interface The internal Write State
Machine

(WSM) automatically executes the algo-

rithms and timings necessary for byte write and
block

erase

operations

including

verifications

thereby unburdening the microprocessor or micro-
controller Writing of memory data is performed in
byte increments typically within 11 ms I

byte

write and block erase currents

are 10 mA typical

30 mA maximum V

byte write and block erase

voltage

is 11 4V to 12 6V

The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation

The RY BY

output gives an additional indicator of

WSM activity providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase
for example) Status polling using RY BY

mini-

mizes both CPU overhead and system power con-
sumption When low RY BY

indicates that the

WSM is performing a block erase or byte write oper-
ation RY BY

high indicates that the WSM is ready

for new commands block erase is suspended or the
device is in deep powerdown mode

Maximum access time is 200 ns (t

ACC

)

over the

commercial temperature range (0 C to a70 C) and
over V

supply voltage range (3 0V to 3 6V and

4 5V to 5 5V) I

active current

(CMOS Read) is

5 mA typical

12 mA maximum

at 5 MHz

3 3V

0 3V

When the CE

and RP

pins are at V

the I

CMOS Standby

mode is enabled

A Deep Powerdown mode is enabled when the
RP

pin is at GND minimizing power consumption

and providing write protection I

current

in deep

powerdown is 0 20 mA typical Reset time of 500 ns
is required from RP

switching high until outputs are

valid to read attempts Equivalently the device has a
wake time of 1 ms from RP

high until writes to the

Command User Interface are recognized by the
28F008SA-L With RP

at GND the WSM is reset

and the Status Register is cleared

28F008SA-L

Table 1 Pin Description

Symbol

Type

Name and Function

� A

INPUT

ADDRESS INPUTS

for memory addresses Addresses are internally

latched during a write cycle

� DQ

INPUT OUTPUT

DATA INPUT OUTPUTS

Inputs data and commands during Command

User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle

INPUT

CHIP ENABLE

Activates the device's control logic input buffers

decoders and sense amplifiers CE

is active low CE

high deselects

the memory device and reduces power consumption to standby levels

INPUT

RESET DEEP POWERDOWN

Puts the device in deep powerdown

mode RP

is active low RP

high gates normal operation RP

also

locks out block erase or byte write operations when active low providing
data protection during power transitions RP

active resets internal

automation Exit from Deep Powerdown sets device to read-array mode

INPUT

OUTPUT ENABLE

Gates the device's outputs through the data buffers

during a read cycle OE

is active low

INPUT

WRITE ENABLE

Controls writes to the Command User Interface and

array blocks WE

is active low Addresses and data are latched on the

rising edge of the WE

pulse

RY BY

OUTPUT

READY BUSY

Indicates the status of the internal Write State

Machine When low it indicates that the WSM is performing a block
erase or byte write operation RY BY

high indicates that the WSM is

ready for new commands block erase is suspended or the device is in
deep powerdown mode RY BY

is always active and does NOT float

to tri-state off when the chip is deselected or data outputs are disabled

BLOCK ERASE BYTE WRITE POWER SUPPLY

for erasing blocks of

the array or writing bytes of each block

NOTE

With V

PPLMAX

memory contents cannot be altered

DEVICE POWER SUPPLY (3 3V

0 3V 5V

10%)

GND

GROUND

28F008SA-L

PRINCIPLES OF OPERATION

The 28F008SA-L includes on-chip write automation
to manage write and erase functions The Write
State Machine allows for 100% TTL-level control
inputs fixed power supplies during block erasure
and byte write and minimal processor overhead with
RAM-like interface timings

After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
28F008SA-L functions as a read-only memory Ma-
nipulation of external memory-control pins allow ar-
ray read standby and output disable operations
Both Status Register and intelligent identifiers can
also be accessed through the Command User Inter-
face when V

PPL

This same subset of operations is also available
when high voltage is applied to the V

pin In addi-

tion high voltage on V

enables successful block

erasure and byte writing of the device All functions
associated with altering memory contents

byte

write block erase status and intelligent identifier
are accessed via the Command User Interface and
verified thru the Status Register

Commands are written using standard microproces-
sor write timings Command User Interface contents
serve as input to the WSM which controls the block
erase and byte write circuitry Write cycles also inter-
nally latch addresses and data needed for byte write
or block erase operations With the appropriate com-
mand written to the register standard microproces-
sor read timings output array data access the Intelli-
gent Identifier codes or output byte write and block
erase status for verification

Interface software to initiate and poll progress of in-
ternal byte write and block erase can be stored in
any of the 28F008SA-L blocks This code is copied
to and executed from system RAM during actual
flash memory update After successful completion of
byte write and or block erase code data reads from
the 28F008SA-L are again possible via the Read Ar-
ray command Erase suspend resume capability al-
lows system software to suspend block erase to
read data and execute code from any other block

FFFFF

64-Kbyte Block

EFFFF

F0000

64-Kbyte Block

DFFFF

E0000

64-Kbyte Block

CFFFF

D0000

64-Kbyte Block

BFFFF

C0000

64-byte Block

AFFFF

B0000

64-Kbyte Block

9FFFF

A0000

64-Kbyte Block

8FFFF

90000

64-Kbyte Block

7FFFF

80000

64-Kbyte Block

6FFFF

70000

64-Kbyte Block

5FFFF

60000

64-Kbyte Block

4FFFF

50000

64-Kbyte Block

3FFFF

40000

64-Kbyte Block

2FFFF

30000

64-Kbyte Block

1FFFF

20000

64-Kbyte Block

0FFFF

10000

64-Kbyte Block

00000

Figure 6 Memory Map

Command User Interface and Write
Automation

An on-chip state machine controls block erase and
byte write freeing the system processor for other
tasks After receiving the Erase Setup and Erase
Confirm commands

the state machine controls

block pre-conditioning and erase returning progress
via the Status Register and RY BY

output Byte

write is similarly controlled after destination address
and expected data are supplied The program and
erase algorithms of past Intel flash memories are
now regulated by the state machine including pulse
repetition where required and internal verification
and margining of data

28F008SA-L

Data Protection

Depending on the application the system designer
may choose to make the V

power supply switcha-

ble (available only when memory byte writes block
erases are required) or hardwired to V

PPH

When

PPL

memory contents cannot be altered

The 28F008SA-L Command User Interface architec-
ture provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V

Additionally all functions are dis-

abled whenever V

is below the write lockout volt-

age V

LKO

or when RP

is at V

The 28F008SA-L

accommodates either design practice and encour-
ages optimization of the processor-memory inter-
face

The two-step byte write block erase Command User
Interface write sequence provides additional soft-
ware write protection

BUS OPERATION

Flash memory reads erases and writes in-system
via the local CPU All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles

Read

The 28F008SA-L has three read modes The memo-
ry can be read from any of its blocks and informa-
tion can be read from the Intelligent Identifier or
Status Register V

can be at either V

PPL

or V

PPH

The first task is to write the appropriate read mode
command to the Command User Interface (array In-
telligent

Identifier

Status

The

28F008SA-L automatically resets to Read Array
mode upon initial device powerup or after exit from
deep powerdown The 28F008SA-L has four control
pins two of which must be logically active to obtain
data at the outputs Chip Enable (CE ) is the device
selection control and when active enables the se-
lected memory device Output Enable (OE ) is the
data input output (DQ

� DQ

) direction control and

when active drives data from the selected memory
onto the I O bus RP

and WE

must also be at

Figure 10 illustrates read bus cycle waveforms

Output Disable

With OE

at a logic-high level (V

) the device out-

puts are disabled

Output pins (DQ

� DQ

) are

placed in a high-impedance state

Standby

logic-high

level

)

places

the

28F008SA-L in standby mode Standby operation
disables much of the 28F008SA-L's circuitry and
substantially reduces device power consumption
The outputs (DQ

� DQ

) are placed in a high-impe-

dence state independent of the status of OE

If the

28F008SA-L is deselected during block erase or
byte write the device will continue functioning and
consuming normal active power until the operation
completes

Table 2 Bus Operations

Mode

Notes

0�7

RY BY

Read

1 2 3

OUT

Output Disable

1 2 3

High Z

Standby

1 2 3

High Z

Deep PowerDown

1 2

High Z

Intelligent Identifier (Mfr)

1 2

89H

Intelligent Identifier (Device)

1 2

A1H

Write

1 2 3 4 5

NOTES
1 Refer to DC Characteristics When V

PPL

memory contents can be read but not written or erased

2 X can be V

or V

for control pins and addresses and V

PPL

or V

PPH

for V

See DC Characteristics for V

PPL

and V

PPH

voltages

3 RY BY

is V

when the Write State Machine is executing internal block erase or byte write algorithms It is V

when

the WSM is not busy in Erase Suspend mode or deep powerdown mode

4 Command writes involving block erase or byte write are only successfully executed when V

PPH

5 Refer to Table 3 for valid D

during a write operation

28F008SA-L

Deep Power-Down

The 28F008SA-L offers a deep power-down feature
entered when RP

is at V

Current draw thru V

is 0 20 mA typical in deep powerdown mode with
current draw through V

typically 0 1 mA During

read modes

RP -low deselects the memory

places output drivers in a high-impedence state and
turns off all internal circuits The 28F008SA-L re-
quires time t

PHQV

(see AC Characteristics-Read-

Only Operations) after return from powerdown until
initial memory access outputs are valid After this
wakeup interval normal operation is restored The
Command User Interface is reset to Read Array and
the upper 5 bits of the Status Register are cleared to
value 10000 upon return to normal operation

During block erase or byte write modes RP

low

will abort either operation Memory contents of the
block being altered are no longer valid as the data
will be partially written or erased Time t

PHWL

after

goes to logic-high (V

) is required before an-

other command can be written

This use of RP

during system reset is important

with automated write erase devices When the sys-
tem come out of reset it expects to read from the
flash memory Automated flash memories provide

status information when accessed during write
erase modes If a CPU reset occurs with no flash
memory reset proper CPU initialization would not
occur because the flash memory would be providing
the status information instead of array data Intel's
Flash Memories allow proper CPU initialization fol-
lowing a system reset through the use of the RP
input In this application RP

is controlled by the

same RESET

signal that resets the system CPU

Intelligent Identifier Operation

The Intelligent Identifier operation outputs the manu-
facturer code 89H and the device code A2H for
the 28F008SA-L The system CPU can then auto-
matically match the device with its proper block
erase and byte write algorithms

The manufacturer- and device-codes are read via
the Command User Interface Following a write of
90H to the Command User Interface a read from
address location 00000H outputs the manufacturer
code (89H) A read from address 00001H outputs
the device code (A2H) It is not necessary to have
high voltage applied to V

to read the Intelligent

Identifiers from the Command User Interface

Table 3 Command Definitions

Command

Cycles

Req'd

Bus

Notes

First Bus Cycle

Second Bus Cycle

Operation Address Data Operation Address Data

Read Array Reset

Write

FFH

Intelligent Identifier

2 3 4

Write

90H

Read

IID

Read Status Register

Write

70H

Read

SRD

Clear Status Register

Write

50H

Erase Setup Erase Confirm

Write

20H

Write

D0H

Erase Suspend Erase Resume

Write

B0H

Write

D0H

Byte Write Setup Write

2 3 5

Write

40H

Write

Alternate Byte Write Setup Write

2 3 5

Write

10H

Write

NOTES
1 Bus operations are defined in Table 2
2 IA

Identifier Address 00H for manufacturer code 01H for device code

Address within the block being erased

Address of memory location to be written

3 SRD

Data read from Status Register See Table 4 for a description of the Status Register bits

Data to be written at location WA Data is latched on the rising edge of WE

IID

Data read from Intelligent Identifiers

4 Following the Intelligent Identifier command two read operations access manufacture and device codes
5 Either 40H or 10H are recognized by the WSM as the Byte Write Setup command
6 Commands other than those shown above are reserved by Intel for future device implementations and should not be

used

28F008SA-L

Write

Writes to the Command User Interface enable read-
ing of device data and Intelligent Identifiers They
also control inspection and clearing of the Status
Register Additionally when V

PPH

the Com-

mand User Interface controls block erasure and byte
write The contents of the interface register serve as
input to the internal state machine

The Command User Interface itself does not occupy
an addressable memory location The interface reg-
ister is a latch used to store the command and ad-
dress and data information needed to execute the
command Erase Setup and Erase Confirm com-
mands require both appropriate command data and
an address within the block to be erased The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written while the Byte Write command consists of
the data to be written and the address of the loca-
tion to be written

The Command User Interface is written by bringing
WE

to a logic-low level (V

) while CE

is low

Addresses and data are latched on the rising edge
of WE

Standard microprocessor write timings are

used

Refer to AC Write Characteristics and the AC Wave-
forms for Write Operations Figure 11 for specific
timing parameters

COMMAND DEFINITIONS

When V

PPL

is applied to the V

pin read opera-

tions from the Status Register Intelligent Identifiers
or array blocks are enabled Placing V

PPH

on V

enables successful byte write and block erase oper-
ations as well

Device operations are selected by writing specific
commands into the Command User Interface Table
3 defines the 28F008SA-L commands

Read Array Command

Upon initial device powerup and after exit from deep
powerdown mode

the 28F008SA-L defaults to

Read Array mode This operation is also initiated by
writing FFH into the Command User Interface Mi-
croprocessor read cycles retrieve array data The
device remains enabled for reads until the Com-
mand User Interface contents are altered Once the
internal Write State Machine has started a block
erase or byte write operation the device will not rec-
ognize the Read Array command until the WSM has
completed its operation The Read Array command
is functional when V

PPL

or V

PPH

Intelligent Identifier Command

The 28F008SA-L contains an Intelligent Identifier
operation initiated by writing 90H into the Command

Table 4 Status Register Definitions

WSMS

ESS

BWS

VPPS

SR 7

WRITE STATE MACHINE STATUS

Ready

Busy

SR 6

ERASE SUSPEND STATUS

Erase Suspended

Erase in Progress Completed

SR 5

ERASE STATUS

Error in Block Erasure

Successful Block Erase

SR 4

BYTE WRITE STATUS

Error in Byte Write

Successful Byte Write

SR 3

STATUS

Low Detect Operation Abort

SR 2�SR 0

RESERVED FOR FUTURE
ENHANCEMENTS

These bits are reserved for future use and
should be masked out when polling the Status
Register

NOTES

RY BY

or the Write State Machine Status bit must first

be checked to determine byte write or block erase com-
pletion before the Byte Write or Erase Status bit are
checked for success

If the Byte Write AND Erase Status bits are set to ``1''s
during a block erase attempt an improper command se-
quence was entered Attempt the operation again

If V

low status is detected the Status Register must be

cleared before another byte write or block erase opera-
tion is attempted

The V

Status bit unlike an A D converter does not

provide continuous indication of V

level The WSM in-

terrogates the V

level only after the byte write or block

erase command sequences have been entered and in-
forms the system if V

has not been switched on The

Status bit is not guaranteed to report accurate feed-

back between V

PPL

and V

PPH

28F008SA-L

User Interface Following the command write a read
cycle from address 00000H retrieves the manufac-
turer code of 89H

A read cycle from address

00001H returns the device code of A1H To termi-
nate the operation it is necessary to write another
valid command into the register Like the Read Array
command the Intelligent Identifier command is func-
tional when V

PPL

or V

PPH

Read Status Register Command

The 28F008SA-L contains a Status Register which
may be read to determine when a byte write or block
erase operation is complete and whether that oper-
ation completed successfully The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In-
terface After writing this command all subsequent
read operations output data from the Status Regis-
ter until another valid command is written to the
Command User Interface

The contents of the

Status Register are latched on the falling edge of
OE

or CE

whichever occurs last in the read cy-

cle OE

or CE

must be toggled to V

before

further reads to update the Status Register latch
The Read Status Register command functions when
V

PPL

or V

PPH

Clear Status Register Command

The Erase Status and Byte Write Status bits are set
to ``1''s by the Write State Machine and can only be
reset by the Clear Status Register Command These
bits indicate various failure conditions (see Table 4)
By allowing system software to control the resetting
of these bits several operations may be performed
(such as cumulatively writing several bytes or eras-
ing multiple blocks in sequence) The Status Regis-
ter may then be polled to determine if an error oc-
curred during that sequence This adds flexibility to
the way the device may be used

Additionally the V

Status bit (SR 3) MUST be re-

set by system software before further byte writes or
block erases are attempted To clear the Status
Register the Clear Status Register command (50H)
is written to the Command User Interface The Clear
Status Register command is functional when V

PPL

or V

PPH

Erase Setup Erase Confirm
Commands

Erase is executed one block at a time initiated by a
two-cycle command sequence

An Erase Setup

command (20H) is first written to the Command User

Interface followed by the Erase Confirm command
(D0H) These commands require both appropriate
sequencing and an address within the block to be
erased to FFH Block preconditioning erase and
verify are all handled internally by the Write State
Machine invisible to the system After the two-com-
mand erase sequence is written to it the 28F008SA-L
automatically outputs Status Register data when
read (see Figure 8 Block Erase Flowchart) The
CPU can detect the completion of the erase event
by analyzing the output of the RY BY

pin or the

WSM Status bit of the Status Register

When erase is completed the Erase Status bit
should be checked If erase error is detected the
Status Register should be cleared The Command
User Interface remains in Read Status Register
mode until further commands are issued to it

This two-step sequence of set-up followed by execu-
tion ensures that memory contents are not acciden-
tally erased Also reliable block erasure can only
occur when V

PPH

In the absence of this high

voltage memory contents are protected against era-
sure If block erase is attempted while V

PPL

the V

Status bit will be set to ``1'' Erase attempts

while V

PPL

PPH

produce spurious results

and should not be attempted

Erase Suspend Erase Resume
Commands

The Erase Suspend command allows block erase
interruption in order to read data from another block
of memory Once the erase process starts writing
the Erase Suspend command (B0H) to the Com-
mand User Interface requests that the WSM sus-
pend the erase sequence at a predetermined point
in the erase algorithm The 28F008SA-L continues
to output Status Register data when read after the
Erase Suspend command is written to it Polling the
WSM Status and Erase Suspend Status bits will de-
termine when the erase operation has been sus-
pended (both will be set to ``1'') RY BY

will also

transition to V

At this point a Read Array command can be written
to the Command User Interface to read data from
blocks other than that which is suspended The only
other valid commands at this time are Read Status
Register (70H) and Erase Resume (D0H) at which
time the WSM will continue with the erase process
The Erase Suspend Status and WSM Status bits of
the Status Register will be automatically cleared and
RY BY

will return to V

After the Erase Resume

command is written to it the 28F008SA-L automati-
cally outputs Status Register data when read (see
Figure 9 Erase Suspend Resume Flowchart) V

must remain at V

PPH

while the 28F008SA-L is in

Erase Suspend

28F008SA-L

Byte Write Setup Write Commands
(40H or 10H)

Byte write is executed by a two-command sequence
The Byte Write Setup command (40H or 10H) is writ-
ten to the Command User Interface followed by a
second write specifying the address and data
(latched on the rising edge of WE ) to be written
The WSM then takes over controlling the byte write
and write verify algorithms internally After the two-
command byte write sequence is written to it the
28F008SA-L automatically outputs Status Register
data when read (see Figure 7 Byte Write Flowchart)
The CPU can detect the completion of the byte write
event by analyzing the output of the RY BY

pin or

the WSM Status bit of the Status Register Only the
Read Status Register command is valid while byte
write is active

When byte write is complete the Byte Write Status
bit should be checked If byte write error is detected
the Status Register should be cleared The internal
WSM verify only detects errors for ``1''s that do not
successfully write to ``0''s The Command User In-
terface remains in Read Status Register mode until
further commands are issued to it If byte write is
attempted while V

PPL

the V

Status bit will

be set to ``1'' Byte write attempts while V

PPL

PPH

produce spurious results and should not be

attempted

EXTENDED BLOCK ERASE BYTE
WRITE CYCLING

Intel has designed extended cycling capability into
its

ETOX

flash

memory

technologies

The

28F008SA-L is designed for 10 000 byte write block
erase cycles on each of the sixteen 64-Kbyte
blocks Low electric fields advanced oxides and
minimal oxide area per cell subjected to the tunnel-
ing electric field combine to greatly reduce oxide
stress and the probability of failure A 20-Mbyte sol-
id-state drive using an array of 28F008SA-Ls has a
MTBF (Mean Time Between Failure) of 3 33 million
hours

(1)

over 60 times more reliable than equivalent

rotating disk technology

AUTOMATED BYTE WRITE

The 28F008SA-L integrates the Quick-Pulse pro-
gramming algorithm of prior Intel Flash Memory de-
vices on-chip using the Command User Interface
Status Register and Write State Machine (WSM)
On-chip integration dramatically simplifies system
software and provides processor interface timings to
the Command User Interface and Status Register
WSM operation internal verify and V

high voltage

presence are monitored and reported via the
RY BY

output and appropriate Status Register

bits Figure 7 shows a system software flowchart for
device byte write The entire sequence is performed
with V

at V

PPH

Byte write abort occurs when RP

transitions to V

or V

drops to V

PPL

Although the

WSM is halted byte data is partially written at the
location where byte write was aborted Block era-
sure or a repeat of byte write is required to initialize
this data to a known value

AUTOMATED BLOCK ERASE

As above the Quick-Erase algorithm of prior Intel
Flash devices is now implemented internally includ-
ing all preconditioning of block data WSM opera-
tion erase success and V

high voltage presence

are monitored and reported through RY BY

and

the Status Register Additionally if a command other
than Erase Confirm is written to the device following
Erase Setup both the Erase Status and Byte Write
Status bits will be set to ``1''s When issuing the
Erase Setup and Erase Confirm commands they
should be written to an address within the address
range of the block to be erased Figure 8 shows a
system software flowchart for block erase

Erase typically takes 2 0 seconds per block The
Erase Suspend Erase Resume command sequence
allows suspension of this erase operation to read
data from a block other than that in which erase is
being performed A system software flowchart is
shown in Figure 9

The entire sequence is performed with V

at V

PPH

Abort occurs when RP

transitions to V

or V

falls to V

PPL

while erase is in progress Block data is

partially erased by this operation and a repeat of
erase is required to obtain a fully erased block

DESIGN CONSIDERATIONS

Three-Line Output Control

The 28F008SA-L will often be used in large memory
arrays Intel provides three control inputs to accom-
modate multiple memory connections Three-line
control provides for
a) lowest possible memory power dissipation
b) complete assurance that data bus contention will

not occur

To efficiently use these control inputs an address
decoder should enable CE

while OE

should be

connected to all memory devices and the system's
READ

control line This assures that only selected

memory devices have active outputs while deselect-
ed memory devices are in Standby Mode RP
should be connected to the system Powergood sig-
nal to prevent unintended writes during system pow-
er transitions Powergood should also toggle during
system reset

(1)

Assumptions 10-Kbyte file written every 10 minutes (20-Mbyte array) (10-Kbyte file) e 2 000 file writes before erase required

(2000 files writes erase)

(10 000 cycles per 28F008SA-L block) e 20 million file writes

(20

file writes)

(10 min write)

(1 hr 60 min) e 3 33

MTBF

28F008SA-L

RY BY

and Byte Write Block Erase

Polling

RY BY

is a full CMOS output that provides a hard-

ware method of detecting byte write and block erase
completion It transitions low time t

WHRL

after a

write or erase command sequence is written to the

28F008SA-L and returns to V

when the WSM

has finished executing the internal algorithm

RY BY

can be connected to the interrupt input of

the system CPU or controller It is active at all times
not tristated if the 28F008SA-L CE

or OE

inputs

are brought to V

RY BY

is also V

when the

device is in Erase Suspend or deep powerdown
modes

290435 � 13

Bus

Command

Comments

Operation

Write

Byte Write

Data

40H (10H)

Setup

Address

Byte to be written

Write

Byte Write

Data to be written
Address

Byte to be written

Standby Read

Check RY BY
V

Ready V

Busy

Read Status Register
Check SR 7
1

Ready 0

Busy

Toggle OE

or CE

update Status Register

Repeat for subsequent bytes

Full status check can be done after each byte or after a
sequence of bytes

Write FFH after the last byte write operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

290435 � 14

Bus

Command

Comments

Operation

Optional

CPU may already have read
Status Register data in WSM

Read

Ready polling above

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4
1

Byte Write Error

SR 3 MUST be cleared if set during a byte write attempt
before further attempts are allowed by the Write State
Machine

SR 4 is only cleared by the Clear Status Register Command
in cases where multiple bytes are written before full status is
checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 7 Automated Byte Write Flowchart

28F008SA-L

290435 � 15

Bus

Command

Comments

Operation

Write

Erase

Data

20H

Setup

Address

Within block to be

erased

Write

Erase

Data

D0H

Address

Within block to be

erased

Standby Read

Check RY BY
V

Ready V

Busy

Read Status Register
Check SR 7
1

Ready 0

Busy

Toggle OE

or CE

update Status Register

Repeat for subsequent bytes

Full status check can be done after each block or after a
sequence of blocks

Write FFH after the last block erase operation to reset the
device to Ready Array Mode

FULL STATUS CHECK PROCEDURE

290435 � 16

Bus

Command

Comments

Operation

Optional

CPU may already have read
Status Register data in WSM

Read

Ready polling above

Standby

Check SR 3
1

Low Detect

Standby

Check SR 4 5
Both 1

Command Sequence

Error

Standby

Check SR 5
1

Block Erase Error

SR 3 MUST be cleared if set during a block erase attempt
before further attempts are allowed by the Write State
Machine

SR 5 is only cleared by the Clear Status Register
Command in cases where multiple blocks are erased
before full status is checked

If error is detected clear the Status Register before
attempting retry or other error recovery

Figure 8 Automated Block Erase Flowchart

28F008SA-L

290435 � 17

Bus

Command

Comments

Operation

Write

Erase

Data

B0H

Suspend

Write

Read

Data

70H

Status Register

Standby

Check RY BY

Read

Ready

Busy

Read Status Register
Check SR 7
1

Ready 0

Busy

Toggle OE

or CE

Update Status Register

Standby

Check SR 6
1

Suspended

Write

Read Array

Data

FFH

Read

Read array data from block
other than that being
erased

Write

Erase Resume

Data

D0H

Figure 9 Erase Suspend Resume Flowchart

Power Supply Decoupling

Flash memory power switching characteristics re-
quire careful device decoupling System designers
are interested in 3 supply current issues standby
current levels (I

) active current levels (I

) and

transient peaks produced by falling and rising edges
of CE

Transient current magnitudes depend on

the device outputs' capacitive and inductive loading
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between each V

and GND and be-

tween its V

and GND These high frequency low

inherent-inductance capacitors should be placed as
close as possible to package leads Additionally for

every 8 devices a 4 7 mF electrolytic capacitor
should be placed at the array's power supply con-
nection between V

and GND The bulk capacitor

will overcome voltage slumps caused by PC board
trace inductances

Trace on Printed Circuit Boards

Writing flash memories while they reside in the tar-
get system requires that the printed circuit board
designer pay attention to the V

power supply

trace The V

pin supplies the memory cell current

for writing and erasing Use similar trace widths and
layout considerations given to the V

power bus

Adequate V

supply traces and decoupling will de-

crease V

voltage spikes and overshoots

28F008SA-L

Transitions and the

Command Status Registers

Byte write and block erase completion are not guar-
anteed if V

drops below V

PPH

If the V

Status bit

of the Status Register (SR 3) is set to ``1'' a Clear
Status Register command MUST be issued before
further byte write block erase attempts are allowed
by the WSM Otherwise the Byte Write (SR 4) or
Erase (SR 5) Status bits of the Status Register will
be set to ``1''s if error is detected RP

transitions to

during byte write and block erase also abort the

operations Data is partially altered in either case
and the command sequence must be repeated after
normal operation is restored Device poweroff or
RP

transitions to V

clear the Status Register to

initial value 10000 for the upper 5 bits

The Command User Interface latches commands as
issued by system software and is not altered by V

or CE

transitions or WSM actions Its state upon

powerup after exit from deep powerdown or after
V

transitions below V

LKO

is Read Array Mode

After byte write or block erase is complete even
after V

transitions down to V

PPL

the Command

User Interface must be reset to Read Array mode via
the Read Array command if access to the memory
array is desired

Power Up Down Protection

The 28F008SA-L is designed to offer protection
against accidental block erasure or byte writing dur-
ing

power

transitions

Upon

power-up

the

28F008SA-L is indifferent as to which power supply
V

or V

powers up first Power supply sequenc-

ing

not

required

Internal

circuitry

the

28F008SA-L ensures that the Command User Inter-
face is reset to the Read Array mode on power up

A system designer must guard against spurious
writes for V

voltages above V

LKO

when V

active Since both WE

and CE

must be low for a

command write driving either to V

will inhibit

writes The Command User Interface architecture
provides an added level of protection since altera-
tion of memory contents only occurs after success-
ful completion of the two-step command sequences

Finally the device is disabled until RP

is brought to

regardless of the state of its control inputs This

provides an additional level of memory protection

Power Dissipation

When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases us-
able battery life because the 28F008SA-L does not
consume any power to retain code or data when the
system is off

In addition

the 28F008SA-L's deep powerdown

mode ensures extremely low power dissipation even
when system power is applied For example porta-
ble PCs and other power sensitive applications us-
ing an array of 28F008SA-Ls for solid-state storage
can lower RP

to V

in standby or sleep modes

producing negligable power consumption If access
to the 28F008SA-L is again needed the part can
again be read following the t

PHQV

and t

PHWL

wake-

up cycles required after RP

is first raised back to

See AC Characteristics

Read-Only and Write

Operations and Figures 10 and 11 for more informa-
tion

28F008SA-L

ABSOLUTE MAXIMUM RATINGS

Operating Temperature

During Read

20 C to a70 C

(1)

During Block Erase Byte Write

0 C to a70 C

Temperature Under Bias

20 C to a80 C

Storage Temperature

65 C to a125 C

Voltage on Any Pin

(except V

and V

)

with Respect to GND

2 0V to a7 0V

(2)

Program Voltage with

Respect to GND during
Block Erase Byte Write

2 0V to a14 0V

(2 3)

Supply Voltage

with Respect to GND

2 0V to a7 0V

(2)

Output Short Circuit Current

100 mA

(4)

NOTICE This data sheet contains information on
products in the sampling and initial production phases
of development The specifications are subject to
change without notice Verify with your local Intel
Sales office that you have the latest data sheet be-
fore finalizing a design

WARNING Stressing the device beyond the ``Absolute

Maximum Ratings'' may cause permanent damage
These are stress ratings only Operation beyond the
``Operating Conditions'' is not recommended and ex-
tended exposure beyond the ``Operating Conditions''
may affect device reliability

NOTES
1 Operating temperature is for commercial product defined by this specification
2 Minimum DC voltage is

0 5V on input output pins During transitions this level may undershoot to

2 0V for periods

20 ns Maximum DC voltage on input output pins is V

0 5V which during transitions may overshoot to V

2 0V for periods

20 ns

3 Maximum DC voltage on V

may overshoot to

14 0V for periods

20 ns

4 Output shorted for no more than one second No more than one output shorted at a time
5 AC specifications are valid at both voltage ranges See DC Characteristics for voltage range specific specification

OPERATING CONDITIONS

Symbol

Parameter

Notes

Min

Max

Unit

Operating Temperature

Supply Voltage

3 00

3 60

Supply Voltage

4 50

5 50

DC CHARACTERISTICS

3 3V

0 3V Read 3 0 � 3 6 Program Erase

Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

Input Load Current

0 5

Max

or GND

Output Leakage Current

0 5

Max

OUT

or GND

CCS

Standby Current

1 3

1 0

2 0

Max

100

Max

0 2V

CCD

Deep PowerDown

0 20

1 2

GND

0 2V

Current

OUT

(RY BY ) e 0 mA

28F008SA-L

DC CHARACTERISTICS

(Continued)

Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

CCR

Read Current

mA V

Max CE

GND

f e 5 MHz I

OUT

0 mA

CMOS Inputs

mA V

Max CE

f e 5 MHz I

OUT

0 mA

TTL Inputs

CCW

Byte Write Current

mA Byte Write In Progress

CCE

Block Erase Current

mA Block Erase In Progress

CCES

Erase Suspend

1 2

mA Block Erase Suspended

Current

PPS

Standby Current

A V

PPD

Deep PowerDown

0 10

5 0

A RP

GND

0 2V

Current

PPR

Read Current

200

A V

PPW

Byte Write Current

mA V

PPH

Byte Write in Progress

PPE

Block Erase Current

mA V

PPH

Block Erase in Progress

PPES

Erase Suspend

200

A V

PPH

Current

Block Erase Suspended

Input Low Voltage

0 5

0 6

Input High Voltage

2 0

0 5

Output Low Voltage

0 4

Min I

2 mA

OH1

Output High Voltage (TTL)

2 4

Min I

e b

2 mA

OH2

Output High Voltage

0 85 V

2 5 mA V

Min

(CMOS)

0 4

e b

100 mA V

Min

PPL

during Normal

0 0

6 5

Operations

PPH

during Erase Write

11 4

12 0

12 6

Operations

LKO

Erase Write Lock

2 0

Voltage

CAPACITANCE

(5)

25 C f e 1 MHz

Symbol

Parameter

Typ

Max

Unit

Condition

Input Capacitance

OUT

Output Capacitance

OUT

28F008SA-L

NOTES
1 All currents are in RMS unless otherwise noted Typical values at V

3 3V V

12 0V T

25 C These currents

are valid for all product versions (packages and speeds)
2 I

CCES

is specified with the device deselected If the 28F008SA-L is read while in Erase Suspend Mode current draw is

the sum of I

CCES

and I

CCR

3 Includes RY BY
4 Block Erases Byte Writes are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

5 Sampled not 100% tested

DC CHARACTERISTICS

5 0V

10%

Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

Input Load Current

1 0

A V

Max

or GND

Output Leakage Current

A V

Max

OUT

or GND

CCS

Standby Current

1 3

1 0

2 0

mA V

Max

100

A V

Max

0 2V

CCD

Deep PowerDown

0 20

1 2

A RP

GND

0 2V

Current

OUT

(RY BY ) e 0 mA

CCR

Read Current

mA V

Max CE

GND

f e 5 MHz I

OUT

0 mA

CMOS Inputs

mA V

Max CE

f e 5 MHz I

OUT

0 mA

TTL Inputs

CCW

Byte Write Current

mA Byte Write In Progress

CCE

Block Erase Current

mA Block Erase In Progress

CCES

Erase Suspend

1 2

mA Block Erase Suspended

Current

PPS

Standby Current

A V

PPD

Deep PowerDown

0 10

5 0

A RP

GND

0 2V

Current

PPR

Read Current

200

A V

PPW

Byte Write Current

mA V

PPH

Byte Write in Progress

PPE

Block Erase Current

mA V

PPH

Block Erase in Progress

PPES

Erase Suspend

200

A V

PPH

Current

Block Erase Suspended

Input Low Voltage

0 5

0 8

Input High Voltage

2 0

0 5

Output Low Voltage

0 45

Min I

5 8 mA

OH1

Output High Voltage (TTL)

2 4

Min I

e b

2 5 mA

OH2

Output High Voltage

0 85 V

e b

2 5 mA V

Min

(CMOS)

0 4

e b

100 mA V

Min

PPL

during Normal

0 0

6 5

Operations

28F008SA-L

DC CHARACTERISTICS

(Continued) V

5 0V

10%

Symbol

Parameter

Notes

Min

Typ

Max

Unit

Test Condition

PPH

during Erase Write

11 4

12 0

12 6

Operations

LKO

Erase Write Lock

2 0

Voltage

NOTES
1 All currents are in RMS unless otherwise noted Typical values at V

5 0V V

12 0V T

25 C These currents

are valid for all product versions (packages and speeds)

2 I

CCES

is specified with the device deselected If the 28F008SA-L is read while in Erase Suspend Mode current draw is

the sum of I

CCES

and I

CCR

3 Includes RY BY
4 Block Erases Byte Writes are inhibited when V

PPL

and not guaranteed in the range between V

PPH

and V

PPL

AC INPUT OUTPUT REFERENCE WAVEFORM

290435 � 7

AC test inputs are driven at 3 0V for a Logic ``1'' and 0 0V for a Logic ``0'' Input timing
begins and output timing ends at 1 5V Input rise and fall times (10% to 90%)

10 ns

AC TESTING LOAD CIRCUIT

(2)

50 pF

Includes Jig

290435 � 8

Capacitance

3 3 kX

AC CHARACTERISTICS

Read-Only Operations

(1)

3 3V

0 3V 5 0V

10%

Versions

28F008SA-150

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Read Cycle Time

150

AVQV

ACC

Address to Output Delay

150

ELQV

to Output Delay

150

PHQV

PWH

High to Output Delay

600

GLQV

to Output Delay

ELQX

to Output Low Z

EHQZ

High to Output High Z

GLQX

OLZ

to Output Low Z

GHQZ

High to Output High Z

Output Hold from Addresses CE

or OE

Change Whichever is First

NOTES
1 See AC Input Output Reference Waveform for timing measurements
2 OE

may be delayed up to t

� t

after the falling edge of CE

without impact on t

3 Sampled not 100% tested

28F008SA-L

AC CHARACTERISTICS

Write Operations

(1)

3 3V

0 3V 5 0V

10%

Versions

28F008SA-L200

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Write Cycle Time

200

PHWL

High Recovery to WE

Going Low

ELWL

Setup to WE

Going Low

WLWH

Pulse Width

VPWH

VPS

Setup to WE

Going High

100

AVWH

Address Setup to WE

Going High

DVWH

Data Setup to WE

Going High

WHDX

Data Hold from WE

High

WHAX

Address Hold from WE

High

WHEH

Hold from WE

High

WHWL

WPH

Pulse Width High

WHRL

High to RY BY

Going Low

100

WHQV1

Duration of Byte Write Operation

5 6

WHQV2

Duration of Block Erase Operation

5 6

0 3

sec

WHGL

Write Recovery

before Read

QVVL

VPH

Hold from Valid SRD RY BY

High

2 6

NOTES
1 Read timing characteristics during erase and byte write operations are the same as during read-only operations Refer to

AC Characteristics for Read-Only Operations

2 Sampled not 100% tested
3 Refer to Table 3 for valid A

for byte write or block erasure

4 Refer to Table 3 for valid D

for byte write or block erasure

5 The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard

Intel flash memory including byte program and verify (byte write) and block precondition precondition verify erase and
erase verify (block erase)

6 Byte write and block erase durations are measured to completion (SR 7

1 RY BY

) V

should be held at

PPH

until determination of byte write block erase success (SR 3 4 5

28F008SA-L

ALTERNATIVE CE -CONTROLLED WRITES

3 3V

0 3V 5 0V

10%

Versions

28F008SA-L200

Unit

Symbol

Parameter

Notes

Min

Max

AVAV

Write Cycle Time

200

PHEL

High Recovery to CE

Going Low

WLEL

Setup to CE

Going Low

ELEH

Pulse Width

VPEH

VPS

Setup to CE

Going High

100

AVEH

Address Setup to CE

Going High

DVEH

Data Setup to CE

Going High

EHDX

Data Hold from CE

High

EHAX

Address Hold from CE

High

EHWH

Hold from CE

High

EHEL

EPH

Pulse Width High

EHRL

High to RY BY

Going Low

100

EHQV1

Duration of Byte Write Operation

EHQV2

Duration of Block Erase Operation

0 3

sec

EHGL

Write Recovery before Read

QVVL

VPH

Hold from Valid SRD RY BY

High

2 5

NOTES
1 Chip-Enable Controlled Writes Write operations are driven by the valid combination of CE

and WE

In systems where

defines the write pulsewidth (within a longer WE

timing waveform) all setup hold and inactive WE

times should

be measured relative to the CE

waveform

2 Sampled not 100% tested
3 Refer to Table 3 for valid A

for byte write or block erasure

4 Refer to Table 3 for valid D

for byte write or block erasure

5 Byte write and block erase durations are measured to completion (SR 7

1 RY BY

) V

should be held at

PPH

until determination of byte write block erase success (SR 3 4 5

28F008SA-L

ORDERING INFORMATION

290435 � 12

VALID COMBINATIONS
E28F008SA-L200

F28F008SA-L200

PA28F008SA-L200

ADDITIONAL INFORMATION

References

Order

Number

28F008SA Datasheet

290429

28F008SA 8 Mbit (1Mbit x 8) Flash Memory SmartDie

Product Specification

271296

AP-359

``28F008SA Hardware Interfacing''

292094

AP-360

``28F008SA Software Drivers''

292095

AP-364

``28F008SA Automation and Algorithms''

292099

ER-27

``The Intel 28F008SA Flash Memory''

294011

ER-28

``ETOX

III Flash Memory Technology''

290412

Revision History

Number

Description

002

Modified Erase Suspend Flowchart
Lowered V

LKO

from 2 2V to 2 0V

Combined V

Standby Current and V

Read Current into One V

Standby Current Spec

with Two Test Conditions (DC Characteristics Table)
Removed

250 Speed Bin

003

PWD renamed to RP

for JEDEC standardization compatibility

Changed I

PPS

standby current specifications from

10 mA to

15 mA in DC Characteristics

tables

004

Changed I

CCR

test condition from f e 8 MHz to f e 5 MHz

Changed I

CCS

Max spec from 50 mA to 2 0 mA

Added I

PPR

spec

Corrected I

PPS

spec typo

Added V

OHZ

(Output High Voltage

CMOS) spec

Changed Operating Temp range (read) from 0 C � 70 C to b20 C � 70 C
Changed V

range from 3 3V

0 3V to 3 15V � 3 6V for Program Erase

Added Byte Write Time spec

005

Changed intelligent identifier device code from A1H to A2H
V

supply voltage (program erase) is now the same as read

CCD

max changed to 1 2 mA

AC Characteristics

Read-only operation t

AVAV

150 ns t

AVQV

150 ns t

ELQV

150 ns

PHQV

600 ns t

GLQV

75 ns

Corrected I

CCS

typical value to read 1 0

Электронный компонент: 28F008SA-L